1. Field of the Invention
The invention relates generally to a sense circuit for a memory storage system and more particularly to a sense circuit in which a bit line pair, supplying the sense signal as a differential voltage, is connected to the control inputs of a differential amplifier whose outputs control the state of a flip-flop serving as a latch circuit.
2. Description of the Prior Art
Present memory systems and in particular those used for computer applications, are manufactured using integrated semiconductor technology, and as such comprise a plurality of specifically organized memory storage cells formed in monolithic semiconductor chips.
Such individual storage cells can be, for example, cross-coupled flip-flops which store information by means of the two switching states they can adopt. Such cross coupled storage cells are integrated in the semiconductor chip and information is written into or read out of the storage cells being accessed, by parallel bit lines connected to the individual storage cells and by word lines arranged perpendicularly to the bit lines.
In a word organized read/write memory, for example, two bit lines are provided for each storage cell in a column, and one word line is associated with each row. As the stored information is read or sensed, the memory system is controlled in such a manner that one or several storage cells emit a read signal identifying their respective switching stage. Generally, the storage cells supply the read signal via a bit line pair connected to the nodes of the storage cells which are made up of cross-coupled flip-flops. The read signal thus consists of a bit line pair. This read signal is sensed, amplified, and transferred to a suitable evaluation circuit.
Many read or sense circuits for such storage systems are known to the prior art. The circuit system used in each case depends, of course, on the memory employed, its organization and the kind of storage cells used, and is adapted to the requirements of the respective application.
In integrated systems, it is common to supply the read signal in the form of a differential voltage on a bit line pair to read amplifiers consisting of two transistors connected as a differential amplifier. The bases of these two transistors are connected to the output signal derived from the read signal is taken from one or both collectors of the two transistors. A read circuit of this kind is described, for example, in "IBM Technical Disclosure Bulletin" Vol. 10, No. 12, May 1968, pp. 1198 and 1999. Many read circuits fitting this description in principle are known from the art and have been used in core storage matrices, as may be seen, for example, in the commonly assigned U.S. Pat. No. 3,617,770 to D. E. Norton et al. issued Nov. 2, 1971.
In integrated storage systems, the amplified read signal obtained is fed to the output of the semiconductor chip. The signal is processed further in storage control circuits outside the semiconductor chip. In up-to-date semiconductor arrangements it is necessary, however, to store the read signal on the semiconductor chip for a longer period of time, for example, for several write cycles, since the necessary control logic can be considerably simplified in this manner.
To effect this temporary storage, the output of the read amplifier is provided with a flip-flop type latch circuit which is integrated on the semiconductor chip.
As the read signals, temporarily stored on the semiconductor chip, have to be transferred at a predetermined time to control circuits outside the semiconductor chip for further processing, it is advisable for output driver circuits, connected to the latch circuit, to also be provided on the chip. In addition to accelerating the signal output, these output driver circuits serve the purpose of preventing control circuits, representing a relatively high load from adversely acting on the semiconductor chip.
Although known arrangements have yielded good results with regard to integration, switching speed, power requirements and noise rejection, they fall short of exacting present day requirements for higher packing densities, lower power dissipation and higher switching speeds.